This is part of a series covering the 3021N communications receiver. This part covers the DSP, and was the third part of the receiver that I replaced with a modern expansion, but this update was also more closely paired with the Synthesizer and Power supply replacement. The demodulator card was finished in the middle of 2020.
Table of Contents
The original card simply performs either envelope or synchronous demodulation based on some control switches. The synchronous LO is either a fixed or variable 8 MHz.
The main issue I sought to eliminate here was the poor performance when DXing AM broadcast, since the receiver had no synchronous AM mode (not surprising).
The new card fits in the card cages like most of the other cards. It takes +5 and +15 V supplies, and its primary function is to accept an 8 MHz IF and generate audio from this.
To support this, the IF is amplified using an AD603 IF VGA, and mixed down to a 12 kHz IF using an AD831 double balanced mixer. The IF if then digitized in a CS4272 audio codec running at 48 kHz.
The mixer local oscillator is generated using an AD9832 32-bit DDS generator, which has extremely high frequency resolution.
The system also takes the "LO3" input, which was originally 8 MHz but was later changed to 20 MHz. This disciplines a 24.576 MHz VCXO through a PLL, and this clock is used to clock all circuitry on the board.
The main processing unit is the ADAU1445 SigmaDSP, and this is paired with a MAX V CPLD from Intel/Altera (my first design using one of these). A STM32F303 mixed signal MCU performs the system control.
A set of high voltage digital inputs are designed to piggyback off the IF filter control lines, which were switched 24 V DC. These are available to the MCU through a CPLD SPI interface.
A F-RAM IC is also present but currently unused since all state is derived from button states.
The S/PDIF interface can be routed to unpopulated coax connectors or through a flat flex cable.
The new demodulator card implements software defined filtering and demodulation, and supports:
- AM Envelope
- AM Synchronous
- DSB and SSB AM demodulation
It also implements controllable 2nd order low pass filters, and AM noise reduction/squelching.
The DSP uses slightly less than 50% of the available resources, leaving plenty of room for expansion.
Frequency fine tuning from the front panel is implemented on this board as well, this is simply done by offsetting the DDS generator frequency.
Basic Demodulator Blocks
The digitized IF is sampled at 48 kHz, and is centered at 12 kHz. The signal is routed through a 20th order IF band-pass filter and AGCed to prevent saturation and compensate for level mismatches. These sharp filters may be removed or slackened later since the new 2nd IF Processor already does this job.
A TODO is to both adjust these filters, but also work out a filter-coefficient calculator; at present these filters are adjusted to match the selected IF filter and mode, but this is done using lookup-tables.
Another TODO is to increase the maximum AF bandwidth to e.g. 4 or 5 kHz, since many signal chain elements here are capped at 3 kHz (sensible when built, but no longer applicable).
The filters and modes are adjusted based on the combination of demodulator modes and filter selections made on the front panel.
The signal is then detected in either a synchronous detector for SSB or CW, or a quadrature PLL detector for AM.
The synchronous detector is just multiplying the IF with a 12 kHz sine wave for SSB or e.g. a 12.5 kHz wave for CW to yield a side-tone.
The quadrature detector is detailed below.
The demodulated signal is routed through a filter selector, then to a DAC going to the DSP card. The filters consist of:
- Synchronous AM Noise Reduction
- Adjustable 2nd Order Low Pass (controlled by the potentiometer knob in all modes except CW)
- Adjustable Q Band Pass (CW, ultra narrow)
This is the SSB/CW detector, it is the most basic type.
The input is multiplied with a tone, yielding a frequency translation. A low pass filter removes the sum output, and DC content is removed before outputting. The incoming LO is either 12 kHz for SSB, or 12.5 kHz nominal for CW.
Quadrature PLL Detector
The quadrature PLL detector is used for AM demodulation (both synchronous and envelope). This detector uses a dual loop carrier recovery system, one of which is shown here, the other is shown later since it extends beyond the DSP.
The principle is to downconvert the IF using a quadrature demodulator, which is two mixers supplied with in-phase and quadrature phase clocks. Each output is then filtered using identical low pass filters.
The I/Q signals can then be used in a various ways to achieve either DSB, envelope detection, or upper/lower sideband detection.
The DSB signal is simply the I branch (the Q branch should be mostly silent).
The envelope detector is the RMS sum of I and Q, this is identical to simply taking the RMS sum of the IF directly.
To detect one sideband and not the other, the SSB outputs are generated by phase shifting the Q branch by 90 degrees using a Hilbert transform, then the I/Q' signal can be added or subtracted to yield a specific sideband.
In order to correct for small phase errors between the external phase locking loop and the actual detector, a Costas loop is implemented in the DSP. This is implemented by multiplying the I and Q signals, low pass filtering the result, then applying this to the VCO clock generator. This is functionally equivalent to using an XOR phase detector in a PLL.
Note that the SSB and DSB outputs work basically exactly like synchronous detectors; they only work well when tuned to exactly the right frequency and phase.
This makes tuning with a synchronous AM receiver exactly like tuning with a DSB receiver, and you can hear the AM carrier whine while tuning. It also means that e.g. CW or RTTY signals sound normal in this mode, except that the PLL system may try to lock to them.
I like to call this a "Precision" Receiver, given that it requires tuning to within +/-50 Hz before the PLL will start tracking properly. In a normal envelope receiver it can be hard to tune exactly onto a station, while in this one it's impossible not to.
Synchronous AM PLL System
The synchronous AM PLL system is rather complex, the core is the quadrature demodulator mentioned above. This can autonomously recover the carrier within a narrow window, and will keep the final phase of the local oscillator in control.
The external loop is split across the DSP, a CPLD, and the main MCU. As established above, the incoming IF is downconverted to 12 kHz using a high precision DDS generator and mixer. The principle here is to allow the DSP to use a "free running" 12 kHz clock (which is clocked off the main radio timebase). The external control loop then compares the DSP's 12 kHz carrier with the recovered carrier from the incoming signal.
To do this, the DSP does carrier detection, and generates a local 12 kHz square wave, which is sent to the CPLD over a basic I2S interface.
Above the DSP blocks to extract the incoming IF carrier is shown. This is simply a high order band pass filter centered at the IF +/-50 Hz, and some AGC is applied to this signal as well.
The result is basically a sine wave, and this is thresholded and output to the CPLD as one channel of a stereo pair. A free running 12 kHz signal makes up the other pair. Since we are operating with square waves at 48 kHz, a dither is applied by generating band-shaped white noise which has no energy around 12 kHz. This added noise reduces the dead-band of the two signals, which is quantized to basically 5 different relative phases by the thresholding and sampling at 48 kHz.
The CPLD accepts this I2S pair and time-aligns the two channels as two square waves, which is applied to a basic PFD inside the CPLD (like a 4046 PC3 it yields a square wave PWM output). The output is a PWM that is low pass filtered and digitized by the STM32F3 ADC.
Above the analog PFD output is shown achieving lock, without noise shaping the signal would have even more significant phase dead band. This phase dead-band is not critical since as mentioned the demodulator circuit has a local Costas loop to correct fine phase errors.
The STM32F3 implements a PID controller that adjusts the DDS generator to maintain a stable phase lock.
This controller has various features beyond a standard PID, such as time-variable gain, basically when it's unlocked it's fairly aggressive, but when achieving lock the gain of the regulator is reduced over time. This allows it to maintain a stable lock for very weak signals, without excessively long initial acquisition times.
Synchronous AM Noise Reduction
The principle of the AM noise reduction is to detect the ratio of carrier to side-band energy, and use this ratio to control a low pass filter and amplitude reduction. This feature requires relatively high precision tuning (within +/-100 Hz) to achieve good performance, though it can be used with both the Sync and Envelope detectors.
It was originally intended to reduce noise pumping when listening to AM broadcast with significant flutter. The problem here is that the level of the AM signal is highly variable, and multipath interference causes various frequency response notches, which is typically audible and sounds like a "phasor" effect.
The real issue is that when this notch hits the carrier, the effective modulation index increases and causes significant distortion in the receiver. The modulation index is the side-band power relative to the carrier power, and with no carrier the modulation index becomes infinite.
This is one of the main reasons to use synchronous AM receivers, which generate their own carrier to use instead of relying on the signal to bring one. However, the radios AGC system will still increase gain when this happens, and this tended to cause increased noise levels when this fading occurred.
So the idea was to attenuate the high frequency noise, and drop the audio level when the carrier disappears. This worked quite well, but it turned out that with some tuning this system also basically cut out the audio entirely when not tuned to an AM signal.
This feature worked so well that it is basically considered the default for this receiver in AM mode, though the standard sync and envelope detectors have non-noise reducing modes for use with the DSP noise reduction modes.
Above the DSP schematic for this functionality is shown. The IF and LO (from the CPLD PD block above) signals are RMS rectified and filtered. The corner frequency and amplitude of the output signal both follow the form of x=(carrier power)/(full band power) where x is either the corner frequency or a scaling factor. The low pass filter is always active, while the gain level is only affected when the ratio is below a threshold.
I am not aware of any other radio implementing this type of noise reduction, feel free to clone it for your own project.
At the same time as integrating this system, the front panel knob changes previously discussed were implemented.
The 8 position rotary switch PCBs were also implemented for the demod and DSP card at this time, replacing whatever was there previously for the DSP (until then it just used a normal switch).